The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to improved methods of forming the buried strap and its quantum conducting barrier (QCB) in deep trench cell capacitors that are fabricated in-situ in the same manufacturing cycle. In addition, these methods allow the formation of new quantum conducting barrier structures by the use of materials such as silicon nitride (Si3N4), silicon oxynitride and the like instead of silicon dioxide (SiO2).
Buried straps (BS) in deep trenches are extensively used in the manufacture of DRAM chips, in particular for devices with groundrules equal or inferior to 0.25 xcexcm. As known for those skilled in the art, in DRAM chips, an array transfer transistor, typically an insulated gate field effect transistor (IGFET) and a storage capacitor are associated to form an elementary memory cell. Basically, a deep trench having a buried plate surrounding its bottom portion is formed in a doped monocrystalline silicon substrate, then a thin dielectric film is conformally deposited thereon to coat the entire interior trench surface and finally the trench is filled with a doped polysilicon by LPCVD as standard. This doped monocrystalline silicon/dielectric film/doped polysilicon fill structure forms the memory cell capacitor. From the silicon surface, a recess is etched down to set the bottom edge of the buried strap. Undoped polysilicon is then deposited into this recessed area to form the buried strap (BS). The buried strap is bordered by the so-called active area (AA) of the monocrystalline substrate and is buried under the shallow trench isolation (STI) region. The surrounding surfaces of the buried strap have an important effect on its conductivity and solid phase transformation during subsequent oxidation and anneal steps (mainly active area oxidation). During these thermal steps, it occurs a recrystallization of the polysilicon of the region of the buried strap which is contiguous to the active area. This local epitaxy induces the propagation of dislocations along the so-called slip lines into the active area and in the substrate which affect cell capacitor performance. Specifically these defects are believed to cause unpredictable changes of the retention time for the capacitor. More precisely, single cell fails (SCF) occurred in some of the tested memory cells, despite the fact that the same bits were not found defective in previous tests. These defects are called Variable Retention Time (VRT) fails. The VRT problem was first identified for 0.25 xcexcm DRAM chips where some memory cells in the array intermittently switched from a high retention state to a low retention state. Physical failure analysis (PFA) showed out that the most of analyzed VRT failed memory cells were impacted by these crystal dislocations in the active area and in the substrate that had been formed during said thermal steps in the course of the wafer processing.
To avoid or better control these VRT fails in memory cells, the use of a quantum conducting barrier layer between said contiguous silicon regions becomes an absolute requirement to maximize DRAM chip device performance. As a result, the buried strap will perfectly connect the IGFET and the capacitor of the memory cell only if after said thermal steps (oxidation and anneal), the dopants implanted in the buried strap diffuse into the active area through the quantum conducting barrier. The diffusion depth into the active area is a critical parameter. If the diffusion is too deep, a parasitic vertical transistor (VT) is formed, otherwise some junction leakages occur. Another critical parameter is the buried strap resistance itself which drives the memory cell access time. Consequently, the choice of the quantum conducting barrier material, the buried strap dopant type and concentration are very important factors for the overall chip reliability.
Starting with the FIG. 1 structure, a conventional buried strap and its quantum conducting barrier (QCB) formation process will be described in conjunction with FIGS. 2A-2F.
FIG. 1 schematically illustrates the starting structure 10 consisting of a p-type silicon substrate 11 with a conventional pad stack formed by a 5 nm thick SiO2 layer 12 and a 220 nm thick Si3N4 pad layer 13. As apparent in FIG. 1, a deep trench referenced 14 has been formed in the substrate 11 by RIE etching as standard. Typically, deep trench 14 has a depth about 7 xcexcm and an oblong section of about 450xc3x97220 nm at the substrate surface. Afterwards, the capacitor dielectric layer 15 is formed and the deep trench is filled with doped polysilicon material 16. After anneal the doped polysilicon fill 16 is recessed to a depth of 1.2 xcexcm to allow the formation of a thermal SiO2 layer 17 and a TEOS SiO2 (pyrolitic) layer 18 forming the so-called collar layer 17/18 which provides a vertical isolation of the cell capacitor. The TEOS layer 18 is etched down to the remaining Si3N4 pad layer 13. Then, a second doped polysilicon layer 19 is deposited, annealed and polished down to the remaining Si3N4 pad layer 13. Polysilicon layer 19 is then recessed 130 nm under the substrate 11 surface. This sets the bottom edge of the buried strap. The collar layer 17/18 is removed from the upper part of the deep trench 14 exposed by a BHF HUANG A/B solution in a DNS 820 tool (Dai Nippon Screen, Yasu, Japan). This isotropic wet etch will recess the oxide materials of collar layer 17/18 slightly under the polysilicon layer 19 level as apparent in FIG. 1. At last, a angled phosphorous implant is performed in the trench sidewall that is exposed to create region 20 which is part of the active area. This step is followed by a 200:1 DHF pre clean in a CFM tool (sold by CFM, Westchester, Pa., USA) to remove 3 nm of the native SiO2 layer. The next steps, i.e. the buried strap and its QCB formation must be performed very quickly e.g. within 1 hour (Q-time) of said pre clean step otherwise a rework would be necessary. In fact, this short processing time is required to avoid native oxidation of the exposed silicon substrate 11.
Now, turning to FIG. 2A, a 1.5 nm thin oxide QCB layer 21 is formed by thermal oxidation at exposed silicon surfaces in a LPCVD vertical thermal reactor (VTR) during boat insertion under ambient atmosphere. The QCB layer 21 is made of thermal SiO2, a material which is an electrical insulator by nature, however, when deposited in very thin film it becomes electrically conductive by a quantum mechanical effect. An adequate reactor is the baseline undoped polysilicon VTR 7000+ manufactured by SVG THERMCO, Orange, Calif., USA.
The current working conditions are:
N2 load lock: no
Q-time: 1 hour
Boat pitch: 0.14 inch
Batch size: 100 wafers centered
Insert temp.: 620xc2x0 C.
Insert time: 10 min
It is important to notice that an uncontrollable oxidation rate is the main drawback of this step.
Now referring to FIG. 2B, a 300 nm thick undoped polysilicon layer 22 is deposited in the same LPCVD VTR tool. As mentioned above, this undoped polysilicon layer 22 is amorphous and will subsequently form the buried strap.
The working conditions are:
Deposition temp.: 550xc2x0 C.
Deposition press.: 0.2 Torr
Deposition time: 167 min
SiH4 flow: 260 sccm
Deposition rate: 18 xc3x85 min
The SiO2 QCB layer 21 will reduce recrystallization (epitaxial regrowth) of the amorphous silicon forming the buried strap and the number of dislocations nucleating at the region 20/polysilicon layer 22 interface. The QCB layer 21 thickness is critical because it has to be thick enough to prevent VRTs and parasitic vertical transistors (VTs) but thin enough to be conductive to insure low buried strap resistance. Consequently, the extreme positions in the LPCVD boat are forbidden, the goal is to have the oxygen level (dose) in layer 21 ranging from 2.2xc3x971015 atoms/cm2 (corresponding to a too thin oxide layer) to 3.0xc3x971015 atoms/cm2 (corresponding to a too thick oxide layer). In these conditions the batch size in the LPCVD VTR tool mentioned above is limited to 100 wafers centered in the boat.
A planarization of the polysilicon layer 22 is performed by chemical-mechanical polishing (CMP) down to the remaining Si3N4 pad layer 13. An adequate tool is the WESTECH 372M polisher manufactured by SPEEDFAM-IPEC, Phoenix, Ariz., USA, At this stage of the fabrication process, the structure is shown in FIG. 2C.
Now turning to FIG. 2D, the undoped polysilicon material of layer 22 is etched until a recess of 40 nm below the substrate 11 surface is obtained. This step which can be performed in an AME 5000 RIE etcher, a tool manufactured by APPLIED MATERIALS, Santa Clara, Calif., USA, is very critical. There will be no buried strap formation if the recess is too deep. On the other hand, there will be no isolation between the buried strap and the gate conductor line (the passing word line) if the recess is too shallow.
A vertical implantation of phosphorous (or arsenic) atoms is performed in the undoped amorphous polysilicon layer 22. To that end, a PI 9500 tool, manufactured by APPLIED MATERIALS, Santa Clara, Calif., USA is adequate. This implantation step affects the buried strap resistance and grain boundaries which in turn could cause recrystallization of the buried strap.
Typical working conditions are:
Phosphorus dose: 5xc3x971013 atoms/cm2 
Energy: 10 KeV
Angle: 0xc2x0
The resulting structure is shown in FIG. 2E where the implanted region bears numeral 23.
Now referring to FIG. 2F, the active area is defined by a photolithography step. Surrounding the active area, the shallow isolation trench (STI) region is formed and filled with SiO2 and TEOS SiO2 materials to form layers 24 and 25. An anneal is performed to densify the TEOS material. These different thermal steps cause the dopants in region 23 to diffuse into region 20 which is part of the active area through the QCB layer 21 forming the xe2x80x9celectricalxe2x80x9d buried strap referenced 26 in FIG. 2F. The electrical buried strap 26 thus results of the merging of regions 20, 21 and 23. Electrical buried strap 26 spreads beyond the phosphorus doped region 20 formed with the previous angled implant as illustrated by the continuous line (vs the dotted line) in FIG. 2F. The QCB layer 21 is getting thinner (and sometimes may even disappear) with migration of dopants from region 23 and solid phase transformation of this region 23 into polycrystalline form.
In summary, the conventional buried strap and its QCB formation process described above in conjunction with FIGS. 2A-2F includes the six following basic steps.
1. Forming the thermal SiO2 quantum conducting barrier layer 21.
2. Depositing the undoped polysilicon layer 22.
3. Polishing the polysilicon layer 22 down to the silicon substrate surface.
4. Recessing the polysilicon layer 22 to 40 nm below the silicon substrate surface.
5. Performing the vertical ion implantation of phosphorous dopants in polysilicon layer 22 to create region 23.
6. Diffusing dopants of region 23 through the quantum conducting barrier layer 21 into region 20 during thermal oxide layer 24 and STI region 25 formation to create the electrical buried strap 26.
FIG. 3 is an enlarged view of structure 10 in the part which is encircled in FIG. 2F when the electrical buried strap 26 is defective. In this case, there is no electrical continuity between regions 20 and 23, the QCB layer 21 being either absent or destroyed. During the thermal steps of oxidation (to form the SiO2 layer 24) and anneal (to densify the TEOS material of the STI region 25), there is produced a local epitaxy phenomena which partially transforms the polysilicon of region 23 in monocristalline silicon as illustrated by region 23A in FIG. 3. This recrystallization creates slip lines 27 that propagate through the region 20 into the substrate bulk. Sometimes, the formation of a large polysilicon grain can occur next to the monocrystalline (single) region 20 at region 23A location which is highly resistive. Accordingly, in both cases, region 23A makes the buried strap defective.
The above described conventional buried strap and its QCB layer fabrication process solved serious reliability problems for 0.25 xcexcm DRAM chips but still raises a severe concern for the next generations (0.2 xcexcm and less groundrules). For these reduced scale devices, oxidizing the region 23/active area interface during the boat insertion into the LPCVD tool to form QCB layer 21 still generates a high VRT level and a high buried strap resistance because of the defects mentioned above by reference to FIG. 3. These defects occur because the thickness of the grown SiO2 of layer 21 is not well controlled and is not tunable in the manufacturing environment. A high buried strap resistance cause single cell fails (SCFs) which provide low temperature reliability fails (if the buried strap resistance is above 12 kOhms) which are added to VRT reliability fails. As the total reliability yield is the multiplication of them, it will become dramatic for these future generations of products. Moreover, before reliability test, pre fuse test showed out other fails due to low retention time and junction leakage along the deep trench and underneath the STI region 25 (referred to herein below as the sub-STI leakage). These failure mechanisms are shown in FIG. 4.
Now turning to FIG. 4, considering the profile A, the extremity of the buried strap 26 does not overlap the drain region 28 of IGFET 29, then a junction leakage occurs at top of the deep trench 14 and provides cell capacitor low retention time. This results of a limited diffusion of the buried strap 26 dopants which is supposed to be related to a QCB layer 21 too thick and/or not permeable enough to dopants. On the contrary, in the case of profile C, the buried strap dopant diffusion is too important, so that leakages along the deep trench 14 and under the STI region 25 occur. The leakage along deep trench 14 is due to a first parasitic NPN transistor created between the buried strap 26 and the buried plate bearing numeral 30 in FIG. 4. This defect is strongly dependent of the buried plate depth (nominal value 1.5 xcexcm). On the other hand, the sub-STI region leakage is due to another parasitic NPN transistor created between two adjacent deep trenches because diffusion regions 20 of the two nearest deep trenches (DT""s) are connected under the STI region 25. This defect is very sensitive to the shallow isolation trench depth (nominal value 0.26 xcexcm). Profile C is related to a QCB layer 21 which is too thin and/or discontinued at the collar layer 17/18 top corner (labeled D in FIG. 4). Profile B shown in FIG. 4 is the right one which overcomes all the problems discussed above.
It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors wherein all the high temperature deposition steps are performed in-situ in the same CVD tool.
It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows high productivity by increasing the number of wafers processed at each run.
It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows manufacturing cost reduction by reducing the number of processing steps.
It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that reduces the chemical contamination from the atmosphere and undesired thermal oxidation effects as a result of a totally clusterized process.
It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows to place the dopants wherever desired in the buried strap with the adequate concentration.
It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors which allows an accurate and total control of both the physical and electrical parameters thereof.
It is still another object of the present invention to provide multilayered quantum conducting barrier structures fabricated by these methods or other as well.
According to the present invention there are described methods of forming the buried strap and its quantum conducting barrier (QCB) in deep trench cell capacitors, wherein the QCB can be either of the single or multiple type. According to a first embodiment of the present invention there is described a method of forming a strap (BS) and its quantum conducting barrier (QCB) to make an electrical connection between two semiconductor regions having a different crystalline nature separated by a region of an insulating material comprising the steps of:
forming a thin continuous layer of undoped amorphous silicon to coat said regions;
forming a QCB layer onto the structure;
forming at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer onto the QCB layer to terminate the strap and its QCB; and,
heating the structure to activate the dopants in the strap to allow an electrical continuity between said semiconductor regions through the QCB by a quantum mechanical effect, wherein all these steps are performed in situ in the same CVD tool.
According to a second embodiment of the present invention there is described a method forming a strap (BS) and its quantum conducting barrier (QCB) to make an electrical connection between two semiconductor regions having a different crystalline nature separated by a region of an insulating material comprising the steps of:
forming a first QCB layer coating said polycrystalline and monocrystalline regions;
forming a thin continuous layer of undoped amorphous silicon to coat said regions;
forming a second QCB layer onto the structure;
forming at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer onto the QCB layer to terminate the strap and its QCB; and,
heating the structure to activate the dopants in the strap to allow an electrical continuity between said semiconductor regions through the QCB by a quantum mechanical effect, wherein all these steps are performed in situ in the same CVD tool.
For instance, they can be conducted by LPCVD with a cageless process. The material forming the QCB is silicon oxynitride, silicon nitride and the like. Nitride based materials can be deposited in thin films, so that they are better controlled than oxide based materials. The ion implantation step which created crystalline defects induced by ions collision is now eliminated. Arsenic is preferred to phosphorus as a dopant because of its slower migration through the QCB layer avoiding thereby parasitic transistors formation. Finally, the LPCVD cageless process permits to place the dopants in desired locations of the buried strap with the adequate concentration.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.